In a Computer System, in addition to the CPU and Main Memory, Input/Output (I/O) is a major functional subsystem. Input/Output System provides a mechanism for communication between the CPU and the external world. I/O subsystem connects the external devices like Keyboard, Mouse, Monitor, Joystick, Pendrive and internal devices like Hard Disk, CD to the Computer. Internet connection is also part of the I/O. We know the functioning principles and characteristics of these devices are widely different from each other. So, what can simplify the technical issues involved in connecting these wide varieties of devices? The answer is to establish applicable communication standard(s).
The I/O communication is simplified to a set of requirements consisting of three parts of Where, What and How? i.e.
- Where? - Identification of the device under communication – The device and location within the device Ex: Select the Printer.
- What? - What is the type of communication? i.e sender? Receiver? (Read/Write?)
- How? - How much to be communicated? ( Number of bytes to/from Memory/file)
The communication is categorized as Intra System and Inter System Communications.
Whether it is Intra or Inter System Communication, a medium is required to carry the communication and also a protocol or standard to carry out the communication successfully. The most familiar one is the Internet as a Wired or Wireless communication. It has protocol standards defined by IEEE. Similarly, every device has a communication protocol which is called the Interface Standard.
The medium and the protocol together is called a BUS. A Bus is a shared communication link consisting of a set of connecting cables/wires which carry signals that are required as per the Interface Standard’s definition. A bus facilitates to achieve the “Where- What –How” of the Communication amongst the various subsystems. We will focus on Internal communication carried out by System bus. A system Bus has three components Address, Data and Control Signals which we have marked many diagrams in the previous chapters (refer figure 20.1)
Few of the important characteristics of interest are Bus Type, Bus Width, Clock Rate, Protocol and Arbitration mechanism.
- Bus Type - Dedicated or Multiplexed
Dedicated - The address and data lines are separate.
Multiplexed - The address and data lines are sent on the same physical cable but at different timings.
- Width – The number of lines that carry Data and Address. More width on address lines increases the addressing range. More width on data lines increases Data Bandwidth.
- Access Protocol - Synchronous or Asynchronous
Synchronous Asynchronous One of the control line is Clock There is no common clock All activities in the bus are synchronized to the clock and at predefined clock cycles The bus transfers information based on handshake protocol. Useful when all the devices in the bus are in the same speed range. Since there is a handshake, any device may interact with any other device. Internal system bus is an example of synchronous bus. Generally used for slow speed device communications.
- Arbitration - The protocol to gain access to the bus amongst the eligible competing devices is called bus arbitration. During the bus operation, there is a Bus Master (Initiator) and a Bus Slave (Responder). Thus a device wanting to initiate communication has to become bus master. Always, the communication happens between two devices. Since there are more devices connected on a bus, there is a bus arbitrator and an identified arbitration mechanism.
- Clock Rate – The speed of the bus is determined by the Synchronous clock. It is a design decision to fix the clock rate.
There are few other physical parameters like how the wires are to be run, what type of connectors to be used, length of the wires, etc. The electrical characteristics define the voltage levels of the signals and the power source. Other Popular internal buses are Peripheral Component Interface Bus (PCI), PCI Express, Accelerated Graphics Port (AGP), VME bus, etc. A Larger variety of standards are there for the External bus which connects Peripherals. To name a few External buses, SCSI, SATA, ATA, USB, FireWire, Centronics, GPIB, IEEE, etc. Bridges are used for connecting buses with different purpose and protocols.
The CPU executes a program in a Fetch-Decode –Execute mode by bringing instructions from Memory. So your program has to get loaded into memory, from the Disk. Generally, both program and executables file is stored in the Disk. This is where the I/O comes into the picture. It is interesting to know the functional requirements of I/O communication with CPU and Memory.
I/O is also a Slave component in the computer. An I/O operation is initiated by CPU and the I/O controllers take care of transferring and completing the I/O operation. An analogy to this is a classroom environment, wherein a teacher (CPU) assigns work; the student (I/O) submits the solution in a Notebook or uploads at the prescribed place(Memory). Probably the student informs the teacher that it is done or it is done for some reason(Interrupt).
- The devices operate at wide-ranging data transfer speed and also many different interface standards. The Keyboard, Mouse have very small data rates and are asynchronous in data transfer to computer. Disk, Solid State Disks have high data rates. USB has a mediocre data rate. And we know each one has a different connector and interface standard.
- It is overloading on the part of CPU to deal with these devices directly. I/O controllers play a bridging role between CPU, Memory and I/O Device by taking care of all kinds of communication.
- Due to heterogeneity of the devices, each device /type of interface requires an I/O Controller (Refer figure 20.1)
- I/O controllers also act as a buffer during data transfer
A data transfer from an I/O device involves:
- Initiate the operation (i.e. addressing the device)
- Direct the device (i.e. communicate the operation to be done and control the data transfer)
- Closing of the IO operations ( i.e notifying the CPU that it is done or not done with status).
To do the above, each IO Controller will typically have Data Register(s), Status Register(s), Control Register(s), Address decoding logic and Control Circuitry as in figure 20.2. The I/O Controller is connected to the system bus. Whenever the I/O controller wants to use the bus, it has to contend and obtain. All communication from the CPU and Memory happens via these registers shown in the diagram. These registers are given a unique address for each I/O controller.
The address decoding logic is connected to the address bus. The value on the address bus indicates the register to be accessed. The decoding logic converts this as an address selection signal to one of these registers.
The control circuitry is connected to the control signals of the system bus. These signals are MEMW, MEMR, IOR, IOW, INTERRUPT, BREQ, etc. These signals ensure the synchronization and validation of address and Data on the bus, demanding the Bus for data transfer, sending interrupt after the normal or abnormal end operation.
The Data Registers take care of Data Transfer. There may be Data In and/or Data Out Registers depending on the device. Also, fast devices like Disk will have a Buffer so that the fast bulk data from the disk is stored and then sent to Memory when the system bus is available.
The Control Register has information like:
- Which is the device to be accessed? (Address of the device)
- What is the Operation (Command) to be carried out on the device?
- Printer Commands – Form Feed for a new page, Print, Line Feed, status check, etc.
- Disk – Seek, Write, Read, Reset, status check
- How this operation is to be carried out?
- Number of Bytes in case of Data Transfer
- What communication is expected by CPU after data transfer to memory
- Mode Settings applicable to devices, etc.
The purpose of Status Register is:
- To have the information about the device being selected
- Whether the device is online and ready?
- If not online have the information about the error from the device. Example - a) Printer may not have a cartridge or paper. This error status is collected in the status register. b) The Disk may not be getting ON
- The status of the data transfer on the device side is stored as a flag in the Status Register.
- Whether the data transfer was successful?
- Data Overrun or Underrun may occur with fast devices like DISK. The buffer operates on PUSH – PULL mode. So in case of an error in PUSH or PULL side Data Overrun or Underrun occurs.
- The status register keeps track of the Word Count pending to be transferred from/to Memory. A Counter is maintained in the I/O controller for this purpose. When Word Count becomes ZERO, it is implied that the data transfer is successfully done.
- Interrupt bit is part of the Status Register. An Interrupt is reasoned with the content of the status register.
This is essentially about allocating addresses to the I/O registers. Each Controller has a set of registers. Two methods in practice are I/O mapped I/O and Memory-mapped I/O.
I/O Mapped I/O
The registers are assigned port numbers and accessed via special instructions namely IN and OUT. This is also Intel’s method. IN is for reading from the Data or Status Registers. OUT is for writing onto the DATA or Command Registers.
Portions of the Memory address space are assigned to I/O device. This method reduces the number of control signals required on the System Bus for READ/WRITE.
|I/O Mapped I/O||Memory-Mapped I/O|
|Exclusive I/O Address space for I/O addressing which are called port addresses||Part of memory address space is reserved for I/O addressing|
|Total addressable space is available for Memory||Available memory is addressable memory space less the reserved space I/O addressing|
|On the Control bus, I/O or Memory operation is differentiated by a separate set of control signals like IOR/IOW, MEMR/MEMW.||On the Control bus, there is only one set of control signals i.e. MEMR/MEMW. Memory or I/O operation is differentiated by decoding the address.|
|The number of lines required for addressing I/O ports is less. Hence address decoding logic on the I/O controllers is smaller and simpler.||The number of lines used for addressing is equal to the maximum addressable space; hence address decoding logic on the I/O controller is larger.|
|Separate I/O instructions like IN/OUT are used for I/O communication.||No such separate instructions used; the same set of STORE/LOAD instructions that are used for memory operations are used for I/O operations too.|
|More opcodes needed in the CPU||Does not increase the opcodes.|